Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).
Several steps are common to most design flows. Initially, a design may typically start at a high level of abstraction, by a designer creating a specification that describes particular desired functionality. This specification, typically implemented by a programming language, such as, for example the C or C++ programming language, describes at a high level the desired behavior of the device. Designers will then often take this specification for the design and create a logical design, often implemented in a netlist, through a synthesis process. The logical design is often referred to as a “register transfer level” (RTL) description or register transfer level design.
A register transfer level design, often implemented by a hardware description language (HDL) such as Verilog, SystemVerilog, or Very High speed hardware description language (VHDL), describes the operation of the device by defining the flow of signals or the transfer of data between various hardware components within the design. More particularly, a register transfer level design describes the interconnection and exchange of signals between hardware registers and the logical operations that are performed on those signals.
The register transfer level design is again transformed, this time into a gate level design. Gate level designs describe the actual physical components such as transistors, capacitors, and resistors as well as the interconnections between these physical components. Often, gate level designs are also implemented by a netlist, such as, for example, a mapped netlist. Lastly, the gate-level design is taken and another transformation is carried out. First by place and route tools that arrange the components described by the gate-level netlist and route connections between the arranged components; and second, by layout tools that generate a layout description having layout “shapes” that may then used to fabricate the electronic device, through for example, an optical lithographic process.
Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is popular for transferring and archiving two-dimensional graphical IC layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in integrated circuit layout designs that are employed to manufacture integrated circuits. Once the microcircuit device design is finalized, the layout portion of the design can be used by fabrication tools to manufacturer the device using a photolithographic process.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design data, after which the mask can be used in a photolithographic process. The image embodied in the layout data is often referred to as the intended or target image or target contours, while the image created in the mask is generally referred to as the mask contours. Furthermore, the image created on the substrate by employing the mask in a photolithographic process is often referred to as the printed image or printed contours.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. A principal reason for declining yields is that as feature sizes shrink, the dominant cause of defects change. At larger process technologies, yield limitation is dominated by random defects. Despite the best clean room efforts, particles still find a way to land on chips or masks, causing shorts or opens. In smaller process technologies, for example the nanometer process technology, the dominant source of yield loss is pattern-dependent effects. These defects are a result of the design's features being smaller than the wavelength of light. As a result, the physical effects of light at these smaller feature sizes must be accounted for.
Various common techniques exist for mitigating these pattern dependant effects. For example, optical process correction (OFC), phase shift masks (PSM) or other resolution enhancement techniques (RET) are commonly employed to prepare a physical layout designs for manufacturing. Additionally, physical verification techniques that assist in accounting for issues such as planarization and antenna effects are also employed on physical layout designs. Although these extensive modifications to the physical layout design resulted in a layout design that was unrecognizable by the designer, the resulting manufactured circuit matched the designer's intent.
These resolution enhancement techniques, including mask data preparation, allow for the manufacture of more modern circuits. However, there is an increased computational cost involved with including these additional processing steps into the design flow. This negatively effects the time in which finalized designs that are ready for tape out can be turned around. Historically, the design processes were viewed as serial. That is, one process was run, followed by a subsequent process, and so on until the finalized design was ready. Various prior methods have sought to parallelize these processes. However, these prior methods operate on the entire data layer. More particularly, parallel operations are not executed until the entire design is ready for the operation.